1. Field of the Invention
The present invention relates to a delay circuit for preventing the reduction in recording accuracy at high speed recording on a disk.
2. Description of the Related Art
Data-recordable optical disk apparatuses and magneto optical disk apparatuses write data onto a disk by recording record marks corresponding to a data modulated signal on the disk with a laser. For example, for CD-Rs, first, data to be recorded is modulated into an EFM signal in an EFM encoder, and this EFM signal is sent to a laser apparatus, and then record marks corresponding to the EFM signal are recorded on a disk.
However, because the record state varies depending on the type of medium to record data thereon and on the rotation speed of the disk, desired record marks cannot be recorded by simply sending the EFM signal to the laser apparatus.
Accordingly, by delaying the timings of the rising and falling of the EFM signal, desired record marks are recorded. In order to delay the EFM signal, a delay line constituted by a plurality of stages of delay cells connected in series is used as disclosed in, for example, the delay circuit of FIG. 2 of Japanese Patent Application Laid-open Publication No. 11-273252. A to-be-delayed signal is inputted into the delay cell of the first stage, and a selector selects one of the outputs from the delay cells of the stages and outputs as a delayed signal. Such a delay circuit is used in the pulse width controller of FIG. 1 of the above Japanese Publication, which is used in the disk recording controller of FIG. 7 of the same.
Each delay cell of the delay line is constituted essentially by two inverters connected in series, and the output of the second inverter is a delayed signal selectable by the selector and is input into the delay cell of the next stage.
In the above-described delay circuit, only the output of the second inverter of the two inverters constituting each delay cell is led out as a delayed signal, and the output of the first inverter is not used. That is, only one delayed signal is obtained from each delay cell. For example, in the case of a delay circuit constituted by a delay line comprising 40 delay cells, only 40 different delayed signals are obtained, and the resolution obtained from the delay amount of each delay cell is no smaller than ( 1/40)×T, where T is the cycle of the reference clock.
Furthermore, since the delay amount of each delay cell needs to be the same, in order to make it less susceptible to the effect of processing accuracy of the semiconductor process, the transistor sizes of the inverter have to be large to a certain degree. Hence, there is a limit to the reduction in the delay amount of each delay cell.
However, where data is recorded on a disk at high speed, with a resolution of such a level, the reduction in record accuracy may be caused.